The present invention generally relates to electric and electronic apparatuses and more particularly to the manufacturing technology of a printed circuit board for use in such electric or electronic apparatuses.
Printed circuit boards are used commonly in electric and electronic apparatuses for carrying various components as well as interconnection patterns connecting the components.
In relation to the ever increasing tendency of mounting density of components on a printed circuit board, recent printed circuit boards are increasingly formed of an electroplating process, rather than conventional screen printing process, such that the conductor patterns are deposited from an electrolyte solution while using a photoresist mask patterned according to the conductor pattern to be formed on the printed circuit board. In the description hereinafter, such circuit boards in which the conductor patterns are formed by an electroplating process rather than screen printing process, is also referred to as a "printed circuit board," according to the conventional practice.
In order to form such a photoresist mask, an exposure mask is employed for patterning an optical beam used for the exposure of the photoresist mask.
FIGS. 1A and 1B show a part of such an exposure mask 11, wherein FIG. 1A shows the exposure mask 11 in a plan view while FIG. 1B shows the exposure mask 11 in a cross sectional view.
Referring to FIGS. 1A and 1B, the exposure mask 11 includes a transparent region 12 for passing the optical beam at the time of exposure and an opaque region 13 that interrupts the optical beam. For example, the exposure mask 11 may be formed on a glass substrate 11 as indicated in FIG. 1B, wherein it will be noted that the opaque region 13 is formed of a metal pattern 15 such as Cr. Thereby, the metal pattern 15 completely interrupts the incident optical beam, and consequently, the optical transmittance of the pattern 15 is 0%. On the other hand, the region outside the metal pattern 15 corresponds to the transparent region 12 where the optical transmittance is nearly 100%.
Using the exposure mask 11, a printed circuit board is manufactured according to a process shown in FIGS. 2A-2F.
Referring to FIG. 2A, an optical irradiation process is conducted upon a substrate 16 that carries thereon a photosensitive layer 17a, while using the exposure mask 11. As already explained, the exposure mask 11 includes the opaque region 13 and the transparent region 12. Thereby, the photosensitive layer 17a is selectively exposed at the region corresponding to the transparent region 12 of the exposure mask, and a resist pattern 17 is obtained as an insulator pattern formed on the substrate 16 as indicated in FIG. 2B, after a developing process that follows the exposure process of FIG. 2A. In the step of FIG. 2B, a baking process is applied upon the resist pattern 17 to convert the same to a stable insulation pattern. Because of the sharp transition of the transmittance of the exposure mask 11 at the boundary between the opaque region 13 and the transparent region 12, the insulation pattern 17 thus formed is defined by a vertical side wall forming a substantially right angle .theta. with respect to a top, major surface thereof.
Next, in the step of FIG. 2C, a thin conductor layer 18 is deposited by a sputtering process and the like, so as to cover the exposed surface of the substrate 16 as well as the side wall and the top surface of the insulation pattern 17.
Further, in the step of FIG. 2D, a resist layer 19 is deposited on the structure of FIG. 2C, followed by a patterning process to form an aperture 20 according to the conductor pattern to be formed on the insulation pattern 17, and an electroplating process is conducted in the step of FIG. 2E while using the conductor layer 18 as an electrode. Thereby, a thick conductor pattern 21a is grown on the insulation pattern 17 selectively in correspondence to the aperture 20.
After the conductor pattern 21a is thus formed, the resist pattern 19 is removed by dissolving into an organic solvent, followed by an ion milling process for removing the extraneous conductor layer 18, and the structure shown in FIG. 2F is obtained where the conductor pattern 21 is formed on the insulation pattern 17 converted from photoresist.
In the conventional process of FIGS. 2A-2F, it should be noted that any cracks associated with mechanical processes such as dicing or sawing applied against the exposed part of the substrate 16, do not propagate to the insulation pattern 17, and the problems associated with such crack propagation is successfully eliminated.
As already noted, the conventional process explained before includes a baking process in the step of FIG. 2B for converting the photoresist pattern 17 into a stable insulation pattern, wherein such a baking process is conducted at a high temperature, typically over 1200.degree. C. for conventional photoresists or over 400.degree. C. for photo-definable polyimides. Associated with such a baking process, the resist pattern 17 tends to shrink as indicated in FIG. 3A and induce a cracking in the substrate 16. When the adherence of the resist pattern 17 upon the substrate 16 is not firm, on the other hand, such a shrinkage of the resist pattern 17 may inducing a coming-off of the pattern 17 from the substrate 16.
Further, the conventional process of FIGS. 2A-2F has a drawback, due to the sharp edge angle .theta., in that the coverage of the photoresist layer 19 over the insulation pattern 17 may become incomplete at the edge of the pattern 17 as indicated in FIG. 4A. In FIG. 4A, it will be noted that the conductor layer 18 is exposed at the edge of the pattern 17.
When the electroplating process is conducted in such a state, it will be noted that the deposition occurs not only at the aperture 20 but also on the exposed edge part of the pattern 17 as indicated in FIG. 4B. In FIG. 4B, it will be noted that a spherical deposit 21a' of conductor is formed simultaneously to the conductor pattern 21a, wherein such a spherical deposit 21a' remains even after the resist layer 19 and the underlying conductor layer 18 is removed. Such an extraneous conductor 21a' causes various problems such as short circuit in the apparatus that uses the printed circuit board.